In a power semiconductor device, current detection elements (sense cells) are provided for the purpose of protecting main cells by detecting excess current, in addition to main elements (main cells) for driving a load in some cases. The sense cells are provided together with the main cells on the same substrate, and when the sense cells detect excess current, the sense cells and the main cells are interrupted, so that these cells can be protected.
Since a smaller number of the sense cells are arranged than that of the main cells in order to avoid reduction in electric efficiency, transistor capacitance is small and a gate insulation film is easily destroyed by a surge voltage of static electricity and the like.
Then, in Patent Document 1, there is provided a structure of a sense cell in which transistor capacitance is made large, by forming a conductive type (p-type) barrier layer different from a semiconductor substrate, and by connecting a barrier layer to a sense terminal, on a semiconductor substrate surface between the sense cell and the main cell, in a MOSFET incorporating the sense cell. Specifically, a detection source electrode connected to a source terminal of the sense cell of the MOSFET is formed in a large area to connect a bonding wire. A large capacitance parasitic capacitor is formed by a thin gate insulation film sandwiched between a large-area gate electrode arranged under a detection source electrode and a p-type barrier layer. With this structure, since a large-capacitance parasitic capacitor is formed between the gate electrode and the detection source electrode, surge resistance to static electricity and the like can be enhanced.